
`timescale 1ps/1ps
module SFI4_TOP(
    input                        SFI4_RESET,

    input                        SFI4_CLK200M_P,
    input                        SFI4_CLK200M_N,

    output[15:0]                 SFI4_0_TXDATA_P,
    output[15:0]                 SFI4_0_TXDATA_N,
    output                       SFI4_0_TXCLK_P,
    output                       SFI4_0_TXCLK_N,
    input                        SFI4_0_TXRFCLK_P,
    input                        SFI4_0_TXRFCLK_N,
    
    input[15:0]                  SFI4_0_RXDATA_P,
    input[15:0]                  SFI4_0_RXDATA_N,
    input                        SFI4_0_RXCLK_P,
    input                        SFI4_0_RXCLK_N,
    
    output                       SFI4_0_RCLK,
    output[63:0]                 SFI4_0_RDATA,
    output                       SFI4_0_TCLK,
    input[63:0]                  SFI4_0_TDATA,



    output[15:0]                 SFI4_1_TXDATA_P,
    output[15:0]                 SFI4_1_TXDATA_N,
    output                       SFI4_1_TXCLK_P,
    output                       SFI4_1_TXCLK_N,
    input                        SFI4_1_TXRFCLK_P,
    input                        SFI4_1_TXRFCLK_N,
    
    input[15:0]                  SFI4_1_RXDATA_P,
    input[15:0]                  SFI4_1_RXDATA_N,
    input                        SFI4_1_RXCLK_P,
    input                        SFI4_1_RXCLK_N,
    
    output                       SFI4_1_RCLK,
    output[63:0]                 SFI4_1_RDATA,
    output                       SFI4_1_TCLK,
    input[63:0]                  SFI4_1_TDATA,



    output[15:0]                 SFI4_2_TXDATA_P,
    output[15:0]                 SFI4_2_TXDATA_N,
    output                       SFI4_2_TXCLK_P,
    output                       SFI4_2_TXCLK_N,
    input                        SFI4_2_TXRFCLK_P,
    input                        SFI4_2_TXRFCLK_N,
    
    input[15:0]                  SFI4_2_RXDATA_P,
    input[15:0]                  SFI4_2_RXDATA_N,
    input                        SFI4_2_RXCLK_P,
    input                        SFI4_2_RXCLK_N,
    
    output                       SFI4_2_RCLK,
    output[63:0]                 SFI4_2_RDATA,
    output                       SFI4_2_TCLK,
    input[63:0]                  SFI4_2_TDATA,



    output[15:0]                 SFI4_3_TXDATA_P,
    output[15:0]                 SFI4_3_TXDATA_N,
    output                       SFI4_3_TXCLK_P,
    output                       SFI4_3_TXCLK_N,
    input                        SFI4_3_TXRFCLK_P,
    input                        SFI4_3_TXRFCLK_N,
    
    input[15:0]                  SFI4_3_RXDATA_P,
    input[15:0]                  SFI4_3_RXDATA_N,
    input                        SFI4_3_RXCLK_P,
    input                        SFI4_3_RXCLK_N,
    
    output                       SFI4_3_RCLK,
    output[63:0]                 SFI4_3_RDATA,
    output                       SFI4_3_TCLK,
    input[63:0]                  SFI4_3_TDATA

    );


wire                    SFI4_IBUF_CLK200M;
wire                    SFI4_CTS_CLK200M;        // clock 200M after clock tree
wire                    SFI4_CLK200M;

IBUFDS             IBUF_CLK200M(
    .O             ( SFI4_IBUF_CLK200M ), 
    .I             ( SFI4_CLK200M_P ), 
    .IB            ( SFI4_CLK200M_N )
    );
BUFG               CTS_CLK200M(
   .O              ( SFI4_CTS_CLK200M ),
   .I              ( SFI4_IBUF_CLK200M )
   );

IDELAYCTRL         SFI4_IDELAYCTRL(
   .RDY            (),
   .REFCLK         ( SFI4_CLK200M ),
   .RST            ( SFI4_RESET)
   );
  assign SFI4_CLK200M   = SFI4_CTS_CLK200M;


SFI4_IF                              INST_SFI4_0(
    .RESET                           ( SFI4_RESET ),
    .OSC_200M                        ( SFI4_CLK200M ),

    .SFI4_TXDATA_P                   ( SFI4_0_TXDATA_P[15:0] ),
    .SFI4_TXDATA_N                   ( SFI4_0_TXDATA_N[15:0] ),
    .SFI4_TXCLK_P                    ( SFI4_0_TXCLK_P ),
    .SFI4_TXCLK_N                    ( SFI4_0_TXCLK_N ),
    .INTERFACE_TXCLK_P               ( SFI4_0_TXRFCLK_P ),
    .INTERFACE_TXCLK_N               ( SFI4_0_TXRFCLK_N ),
    
    .SFI4_RXDATA_P                   ( SFI4_0_RXDATA_P[15:0] ),
    .SFI4_RXDATA_N                   ( SFI4_0_RXDATA_N[15:0] ),
    .SFI4_RXCLK_P                    ( SFI4_0_RXCLK_P ),
    .SFI4_RXCLK_N                    ( SFI4_0_RXCLK_N ),

    .SFI4_RCLK                       ( SFI4_0_RCLK ),
    .SFI4_RDATA                      ( SFI4_0_RDATA[63:0] ),
    .SFI4_TCLK                       ( SFI4_0_TCLK ),
    .SFI4_TDATA                      ( SFI4_0_TDATA[63:0] ),

    .SFI_MANUAL_DELAY_INC            (  ),
    .SFI_MANUAL_DELAY_DEC            (  ),
    .SFI_TRAINING_DONE               (  ),
    .SFI_IDELAY_READY                (  )
    );



SFI4_IF                              INST_SFI4_1(
    .RESET                           ( SFI4_RESET ),
    .OSC_200M                        ( SFI4_CLK200M ),

    .SFI4_TXDATA_P                   ( SFI4_1_TXDATA_P[15:0] ),
    .SFI4_TXDATA_N                   ( SFI4_1_TXDATA_N[15:0] ),
    .SFI4_TXCLK_P                    ( SFI4_1_TXCLK_P ),
    .SFI4_TXCLK_N                    ( SFI4_1_TXCLK_N ),
    .INTERFACE_TXCLK_P               ( SFI4_1_TXRFCLK_P ),
    .INTERFACE_TXCLK_N               ( SFI4_1_TXRFCLK_N ),
    
    .SFI4_RXDATA_P                   ( SFI4_1_RXDATA_P[15:0] ),
    .SFI4_RXDATA_N                   ( SFI4_1_RXDATA_N[15:0] ),
    .SFI4_RXCLK_P                    ( SFI4_1_RXCLK_P ),
    .SFI4_RXCLK_N                    ( SFI4_1_RXCLK_N ),

    .SFI4_RCLK                       ( SFI4_1_RCLK ),
    .SFI4_RDATA                      ( SFI4_1_RDATA[63:0] ),
    .SFI4_TCLK                       ( SFI4_1_TCLK ),
    .SFI4_TDATA                      ( SFI4_1_TDATA[63:0] ),

    .SFI_MANUAL_DELAY_INC            (  ),
    .SFI_MANUAL_DELAY_DEC            (  ),
    .SFI_TRAINING_DONE               (  ),
    .SFI_IDELAY_READY                (  )
    );



SFI4_IF                              INST_SFI4_2(
    .RESET                           ( SFI4_RESET ),
    .OSC_200M                        ( SFI4_CLK200M ),

    .SFI4_TXDATA_P                   ( SFI4_2_TXDATA_P[15:0] ),
    .SFI4_TXDATA_N                   ( SFI4_2_TXDATA_N[15:0] ),
    .SFI4_TXCLK_P                    ( SFI4_2_TXCLK_P ),
    .SFI4_TXCLK_N                    ( SFI4_2_TXCLK_N ),
    .INTERFACE_TXCLK_P               ( SFI4_2_TXRFCLK_P ),
    .INTERFACE_TXCLK_N               ( SFI4_2_TXRFCLK_N ),
    
    .SFI4_RXDATA_P                   ( SFI4_2_RXDATA_P[15:0] ),
    .SFI4_RXDATA_N                   ( SFI4_2_RXDATA_N[15:0] ),
    .SFI4_RXCLK_P                    ( SFI4_2_RXCLK_P ),
    .SFI4_RXCLK_N                    ( SFI4_2_RXCLK_N ),

    .SFI4_RCLK                       ( SFI4_2_RCLK ),
    .SFI4_RDATA                      ( SFI4_2_RDATA[63:0] ),
    .SFI4_TCLK                       ( SFI4_2_TCLK ),
    .SFI4_TDATA                      ( SFI4_2_TDATA[63:0] ),

    .SFI_MANUAL_DELAY_INC            (  ),
    .SFI_MANUAL_DELAY_DEC            (  ),
    .SFI_TRAINING_DONE               (  ),
    .SFI_IDELAY_READY                (  )
    );


SFI4_IF                              INST_SFI4_3(
    .RESET                           ( SFI4_RESET ),
    .OSC_200M                        ( SFI4_CLK200M ),

    .SFI4_TXDATA_P                   ( SFI4_3_TXDATA_P[15:0] ),
    .SFI4_TXDATA_N                   ( SFI4_3_TXDATA_N[15:0] ),
    .SFI4_TXCLK_P                    ( SFI4_3_TXCLK_P ),
    .SFI4_TXCLK_N                    ( SFI4_3_TXCLK_N ),
    .INTERFACE_TXCLK_P               ( SFI4_3_TXRFCLK_P ),
    .INTERFACE_TXCLK_N               ( SFI4_3_TXRFCLK_N ),
    
    .SFI4_RXDATA_P                   ( SFI4_3_RXDATA_P[15:0] ),
    .SFI4_RXDATA_N                   ( SFI4_3_RXDATA_N[15:0] ),
    .SFI4_RXCLK_P                    ( SFI4_3_RXCLK_P ),
    .SFI4_RXCLK_N                    ( SFI4_3_RXCLK_N ),

    .SFI4_RCLK                       ( SFI4_3_RCLK ),
    .SFI4_RDATA                      ( SFI4_3_RDATA[63:0] ),
    .SFI4_TCLK                       ( SFI4_3_TCLK ),
    .SFI4_TDATA                      ( SFI4_3_TDATA[63:0] ),

    .SFI_MANUAL_DELAY_INC            (  ),
    .SFI_MANUAL_DELAY_DEC            (  ),
    .SFI_TRAINING_DONE               (  ),
    .SFI_IDELAY_READY                (  )
    );
   
   
endmodule